JIA Hua-yu, CHEN Gui-can, ZHANG Hong

" /> A new structure of substage in pipelined analog-to-digital converters

中国邮电高校学报(英文) ›› 2009, Vol. 16 ›› Issue (1): 86-90.doi: 10.1016/S1005-8885(08)60184-3

• Electronics • 上一篇    下一篇

A new structure of substage in pipelined analog-to-digital converters

贾华宇,CHEN Gui-can, ZHANG Hong   

  1. Institute of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, China
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2009-02-26
  • 通讯作者: 贾华宇

A new structure of substage in pipelined analog-to-digital converters

JIA Hua-yu, CHEN Gui-can, ZHANG Hong   

  1. Institute of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, China
  • Received:1900-01-01 Revised:1900-01-01 Online:2009-02-26
  • Contact: JIA Hua-yu

摘要:

The article presents a new (1+1)-bit/stage structure for pipelined analog-to-digital converters (ADC). When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators’ decision levels. The ADC implemented in Semiconductor Manufactory International Corporation (SMIC) 0.18 μm CMOS process consumes 210 mW and occupies a chip area of 3.2×3.7 mm2.

关键词:

digital correction, pipelined ADC, residue voltage?, operational amplifier

Abstract:

The article presents a new (1+1)-bit/stage structure for pipelined analog-to-digital converters (ADC). When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators’ decision levels. The ADC implemented in Semiconductor Manufactory International Corporation (SMIC) 0.18 μm CMOS process consumes 210 mW and occupies a chip area of 3.2×3.7 mm2.

Key words:

digital correction, pipelined ADC, residue voltage?, operational amplifier